The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods for forming a cut between interconnects and structures with cuts between interconnects.
A back-end-of-line interconnect structure may be used to connect device structures, which were fabricated on a substrate during front-end-of-line processing, with each other and with the environment external to the chip. Self-aligned multiple patterning processes used to form an interconnect structure involve linear mandrels acting as sacrificial features that establish a feature pitch. Non-mandrel lines are arranged as linear spaces between sidewall spacers that are formed adjacent to the sidewalls of the mandrels. After the mandrels are pulled to define mandrel lines, the sidewall spacers are used as an etch mask to etch a pattern predicated on the mandrel lines and the non-mandrel lines into an underlying hardmask. The pattern is subsequently transferred from the hardmask to an interlayer dielectric layer as trenches in which the interconnects of the interconnect structure are formed.
Mandrel cuts may be formed in the mandrels in order to section the mandrels and define discontinuities between the different sections. Non-mandrel cuts may also be formed as discontinuities along non-mandrel lines and may include portions of the spacer material used to form the sidewall spacers. The mandrel cuts and non-mandrel cuts are included in the pattern that is transferred to the hardmask and subsequently transferred from the hardmask to form the trenches in the interlayer dielectric layer. The mandrel cuts and non-mandrel cuts appear in the interconnect structure as adjacent interconnects that are aligned and spaced apart at their respective ends with a tip-to-tip spacing related to the dimension of the discontinuity.
The need for double patterning can be eliminated through the use of extreme ultraviolet (EUV) patterning, which is capable of directly patterning a resist. The resist may then be used in conjunction with an etching process to form a dense sea of narrow lines and trenches in an interlayer dielectric layer. However, the formation of cuts in the interconnects formed in the narrow trenches presents technical challenges with respect to techniques, as well as materials.
Improved methods for forming a cut between interconnects and structures with cuts are therefore needed.